SST’s Smartbit™ based OTP Memory Technology
It all begins with expertise, imagination and dedication...
The SST Smartbit™ cell generates and confines the breakdown voltage entirely in the memory core allowing the unprogrammed cells to have the native reliability of the process while only the programmed cells see high voltage.
To ensure that a programmed cell has achieved hard breakdown, Smartbit™ applies the high voltage until it detects the current signature of hard breakdown. Complete bit cell programming and the longest OTP NVM data retention are guaranteed.
Smartbit™ technology avoids the data retention issues associated with floating gate designs.
Unlike polysilicon or laser fuses, it is possible to route over IP based upon Smartbit™ IP, thus consuming no additional chip area.
Would you like more information on SST’s Smartbit™ OTP?
Download the Dynamic Programming white paper.