SST - SILICON STORAGE TECHNOLOGY

Silicon Storage Technology

Second Generation - ESF2

Second Generation - ESF2

Superflash_Tech_Gen2

The second generation SuperFlash® cell has been used in both stand-alone and embedded flash memory products since 2006. This self-aligned, double-poly cell also uses split-gate architecture and has floating-gate poly as a storage element with 3 nodes for Read, Erase, and Program operations:

  • Word-line (WL)
  • Source-line (SL)
  • Bit-line (BL)

Ease of Integration

The beauty of the second generation SuperFlash® lies in the simplicity of forming the memory cell in a given logic process. The field enhanced tunneling injector on the floating poly is formed using standard CMOS oxidation and etching processes. The WL poly uses the standard CMOS logic poly. Drain and source are created with logic junction formation. The advancement of the ESF2 cell comes with self-aligning processing steps in forming the floating-gate, source line poly, and WL poly, thus reducing the number of masks required to create the memory cell. The floating-gate element is self-aligned to the formation of active. The source line poly and WL poly are self-aligned to floating-gate poly and dielectric spacers. The first generation cell has been scaled from 180nm to 110nm technology nodes.

ESF2 Cell Operations

  • Erase: Erase operation uses ploy-to-poly tunneling with the field enhancing poly injector.
  • Program: Program uses Source Side Injection (SSI) for fast and efficient operation.
  • Read: Read operation is performed with low voltage Vcc, and doesn’t need any high voltages.

ESF2 Array Architecture and Functional Operation

The second generation SuperFlash® cell retains the simple operation and array architecture of the first generation technology. The SuperFlash memory array is arranged in cross-point architecture with rows of word-lines and columns of bit lines. The rows can be segmented into big blocks or small sectors. During the Erase operation, a voltage is applied to the word-lines (WL) that erases all the cells in one pulse. Cells can be programmed by bits or by page with relatively low voltage on Source-line (SL). To create channel hot electrons at the gap region between the select-gate and the floating-gate channels during program, the select transistor is slightly turned on with a small voltage on the select-gate and a small programming current applied to the bit line. The memory cell is read with Vcc on the word-line and a reference voltage on the bit line.