Third Generation - ESF3
The third generation SuperFlash® cell has been used in both stand-alone and embedded flash memory products for over 3 years. As of mid-2012, SST and its partners have shipped more than 400 million units based on this architecture. This self-aligned triple-poly cell uses split-gate architecture, has floating-gate poly as a storage element and has 5 nodes for Read, Erase, and Program operations:
- lD-line (WL)
- Source-line (SL)
- Bit-line (BL)
- Coupling Gate (CG)
- Erase Gate (EG)
Ease of Integration
The process of forming the third generation cell is simpler than that of the second generation cell, despite the presence of the additional nodes to enhance the scaling and performance. The floating-gate is self-aligned to both the active and coupling gate. Both word-line and erase gate are created through logic poly-silicon deposition. Drain and source junctions come from standard CMOS logic process.
ESF3 Cell Operations
- Erase: Erase operation uses ploy-to-poly tunneling with the field enhancing poly injector.
- Program: Program uses Source Side Injection (SSI) for fast and efficient operation.
- Read: Read operation is performed with low voltage Vcc, and doesn’t require any high voltages.
ESF3 Array Architecture and Functional Operation
The third generation SuperFlash® cell retains the simple operation and array architecture of the first generation technology. The SuperFlash memory array is still arranged in cross-point architecture with rows of word-lines and columns of bit lines. The rows can be segmented into big blocks or small sectors. During Erase operation, a voltage is applied to the Erase Gate (EG) that erases all the cells in one pulse. Cells can be programmed by bits or page with relatively low voltage on Source-line (SL). To create channel hot electrons at the gap region between the select-gate and the floating-gate channels during program, the Word-line transistor (WL) is slightly turned on with a small voltage on the select-gate and a small programming current applied to the bit line. The memory cell is read with Vcc on the word-line and a reference voltage on the bit line.